You will contribute to the design and development of CPU hardware at the register transfer level (RTL), focusing on high-performance computing for artificial intelligence and machine learning applications. This role offers direct involvement in RTL implementation, debugging, and architectural improvements under the guidance of experienced hardware engineers.
Key Responsibilities
- Write and maintain RTL code for CPU components using Verilog, VHDL, or SystemVerilog
- Analyze and troubleshoot existing CPU designs to support feature enhancements and performance optimization
- Support the development of infrastructure and tools used in RTL simulation, verification, and performance analysis environments
Qualifications
Applicants should be in their final year of study toward a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with strong academic performance. Required skills include experience with hardware description languages and scripting, along with coursework or projects involving SystemVerilog and verification techniques such as testbench development, simulation, coverage analysis, and debugging.
Preferred Background
- Academic or internship experience in computer architecture
- Familiarity with assembly language and scripting tools used in RTL workflows
Work Environment
This is a full-time, onsite position based in either Santa Clara, CA or Austin, TX, requiring 40 hours per week. The team values collaboration, technical rigor, and a drive to solve complex engineering challenges in the AI domain. You will receive mentorship from senior engineers and work directly on technologies central to next-generation AI platforms.
Compliance Note
Eligibility to handle U.S. export-controlled technology is required. Employment may depend on citizenship, permanent residency, or the ability to obtain authorization from the U.S. Department of Commerce. Offers are contingent on compliance with the Export Administration Regulations.
