Axiom Software Solutions Limited is hiring an Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer. You will be responsible for verifying analog/mixed-signal designs through behavioral modeling, testbench development, and simulation. The role involves direct collaboration with circuit designers and layout engineers to influence design changes and ensure functional specifications are met.

What You'll Do

Extract modeling specifications from designers.
Develop Analog/Mixed-Signal models in System-Verilog.
Develop UVM Testbenches and test cases.
Run simulations and fix behavioral models working with a Circuit designer.
Develop timing models for circuits working with a layout engineer.
Determine whether anomalous symptoms are caused by errors in specifications, models, testbench, or design.
Support integration of composite models into larger composite models maintained by other groups.

What We're Looking For

Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, and combinatorial logic.
Good understanding of digital design for mixed signal control loops.
Ability to design Verilog / Verilog-A code to control analog circuits (e.g., band-gap, PLL, Amplifier, Filters).
Familiarity with behavioral Verilog code for an analog circuit.
Ability to write thorough test benches for digital and AMS simulators.
Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating.
Familiarity with timing closure and static timing analysis tools.
Experience with scan chain vector generation and verification.