NXP is looking for a Principal Engineer to take on a critical STA leadership role. You will be responsible for bringing timing convergence for SOCs, driving design changes, and owning end-to-end timing closure and signoff.
What You'll Do
- Bring timing convergence for SOC.
- Drive design changes.
- Be responsible for end-to-end timing closure and timing signoff.
- Own driving timing signoff criteria, design clocking, constraints development and validation.
- Interface with critical domains like IP, Functional Integration, DFT & Verification.
- Work closely with the Physical Implementation team for providing feedback, timing convergence and ECO creation, timing/noise model build, GLS support and final timing signoff.
- Understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing constraints with multiple clocks.
- Own bottom-up partition-level integration and top-down design partitions constraints.
- Contribute in flow/methodology related scripting as part of design implementation.
What We're Looking For
- Ability to understand advanced digital design architectures and clocking structures to help manage Functional/Scan/MBIST timing constraints with multiple clocks.
- Expertise in SOC IO constraints development.
- Expertise in Advanced Timing Analysis, Debug and timing convergence, ECO creation with signal integrity & EM/IR.
- Knowledge about SDF, GLS, and ability to debug timing failures.
- Hands-on experience working on technology nodes like 28nm, 16nm, 10nm, 7nm.
- Good knowledge of EDA tools from RC, DC, PT, PTSI.
- Good knowledge of Synthesis, Floor planning, place & route, power and clock distribution, pin placement and timing analysis.
Technical Stack
- RC
- DC
- PT
- PTSI
Team & Environment
You will interface with critical domains like IP, Functional Integration, DFT & Verification while working closely with the Physical Implementation team.
Work Mode
This position is based in India.
