Responsibilities
- Understand complex digital architectures and multi-clock systems to manage functional, scan, and MBIST timing requirements.
- Develop and manage input/output constraints for system-on-chip designs.
- Lead bottom-up integration of design partitions and manage top-down constraint propagation.
- Perform advanced timing analysis, debug timing violations, and ensure convergence with ECOs that account for signal integrity and EM/IR effects.
- Demonstrate proficiency in SDF and gate-level simulation, including debugging of timing failures.
- Apply hands-on experience with semiconductor technology nodes including 28nm, 16nm, 10nm, and 7nm.
- Possess strong working knowledge of EDA tools such as RC, DC, PT, and PTSI.
- Apply deep understanding of synthesis, floor planning, place and route, power distribution, clock networks, pin placement, and timing validation.
- Contribute to the development of design implementation flows and methodologies through scripting and automation.
