The Data & IO Design Engineer will design and develop high-speed IO and data interface circuits for NAND memory technologies. This role involves close collaboration with system architects, RTL designers, and hardware teams to define interface requirements and optimize signal integrity across silicon, package, and board levels. The engineer will support silicon bring-up, debug, and post-silicon characterization in a globally distributed technology environment.
Responsibilities
- Design and develop high-speed IO and data interface circuits, including drivers, receivers, clocking, and serialization/deserialization (SerDes) components.
- Collaborate with system architects and RTL designers to define interface specifications, signal integrity constraints, and performance goals.
- Conduct circuit- and system-level simulations using tools such as SPICE, IBIS-AMI, and HSPICE to verify signal integrity and timing under process, voltage, and temperature variations.
- Work with package and board design teams to co-optimize high-speed signal paths for performance, reliability, and manufacturability.
- Support silicon bring-up, debugging, and validation of IO interfaces in both silicon and system-level test environments.
- Participate in post-silicon characterization, tuning, and root cause analysis of signal integrity and margin issues.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or a related field.
- Minimum of 3 years of experience in high-speed digital or mixed-signal IO design.
- Solid understanding of high-speed signaling principles such as impedance matching, crosstalk, jitter, and equalization techniques.
- Proven experience with EDA tools for layout-aware simulation, signal integrity analysis, and timing verification.
- Familiarity with high-speed interface standards including PCIe, ONFI, LPDDR, or similar memory protocols.
Nice to Have
- Experience in designing IO interfaces for NAND Flash, SSD controllers, or other high-bandwidth memory and storage systems.
- Knowledge of packaging parasitics, board-level parasitic effects, and system-level co-design methodologies.
- Proficiency in scripting languages such as Python, Perl, or Tcl for simulation automation and data analysis.
- Strong problem-solving abilities and experience working across cross-functional hardware and validation teams.
Tech Stack
SPICE, IBIS-AMI, HSPICE, EDA tools, PCIe, ONFI, LPDDR, Python, Perl, Tcl
Compensation
The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by skills, experience, qualifications, and geographic location.
Work Arrangement
local-country — Rancho Cordova, California, USA, Other U.S. facilities, International locations in Asia, Europe, and the Americas
Team
Cross-functional collaboration with system architects, RTL designers, package and board design teams, and hardware validation teams.
- Diverse, equitable, and inclusive culture
- Embraces individual uniqueness
- One Team mindset
- Customer inspired
- Trusting
- Innovative
- Team-oriented
- Inclusive
- Results driven
- Collaborative
- Passionate
- Flexible
Additional Information
- Headquartered in Rancho Cordova, California.
- Global presence in Asia, Europe, and the Americas.
- Company aspires to be the #1 NAND memory company in the world.
- Combines established technology company elements with start-up agility and entrepreneurial mindset.
