Join a team at the forefront of semiconductor innovation, where you'll take ownership of the full physical design flow for next-generation LPU architectures. In this role, you'll lead critical path activities from synthesis through tapeout, ensuring robust design closure and silicon integrity.
Key Responsibilities
- Lead full-flow physical implementation at both block and top-level, including synthesis, floorplanning, place and route, timing constraint development, UPF implementation, and logical equivalency checking.
- Collaborate with architecture, logic design, and IP teams to resolve integration challenges, eliminate bottlenecks, and optimize PPA across complex multi-voltage designs.
- Drive design closure with sign-off teams, ensuring compliance with all verification requirements for successful GDSII delivery.
- Develop and deploy data-driven EDA methodologies in partnership with CAD, leveraging automation and AI-enhanced techniques to improve design efficiency and quality.
Qualifications
- Bachelor's degree in Electrical or Computer Engineering, or equivalent industry experience, with 5+ years of hands-on physical design for large-scale SoCs on advanced nodes.
- Proven success in managing RTL-to-GDSII flows, including synthesis, CTS, routing, extraction, and physical/electrical sign-off.
- Strong expertise in low-power design using UPF/CPF, formal verification (LEC), and multi-domain power management.
- Deep knowledge of clock tree synthesis and multi-corner, multi-mode timing analysis.
- Experience optimizing power, performance, and area across the design lifecycle.
- Proficiency in EMIR analysis, power grid design, and ECO implementation for timing closure.
- Skilled in DFT integration at the block level using industry best practices.
- Expertise with industry-standard EDA tools and strong scripting ability in TCL, Python, or Perl.
Preferred Experience
- Background in integrating high-speed interfaces such as PCIe, CXL, C2C, or die-to-die interconnects.
Compensation & Benefits
This role offers a competitive base salary, equity participation, and a comprehensive benefits package including health coverage, paid time off, and relocation support. The company fosters a diverse, inclusive, and collaborative environment committed to engineering excellence and equal opportunity for all.
