NVIDIA is looking for a Senior Physical Design Engineer to join our LPU chip design team. You will contribute to our innovative chip designs, taking ownership of the full-flow physical design process and collaborating closely with cross-functional teams to achieve optimal performance, power, and area.
What You'll Do
- Own full-flow physical design, including Synthesis, floorplanning, place & route, timing constraints, UPF, and LEC at block and top levels.
- Partner with IP, Front-End, and Architecture teams to streamline IP integration and drive PPA (Power, Performance, Area) optimizations.
- Lead design closure and tapeout execution, ensuring 100% verification compliance for GDSII handoff.
- Architect data-driven EDA flows and methodologies, implementing automated enhancements that improve design cycle efficiency.
What We're Looking For
- B.S. in Electrical/Computer Engineering or equivalent with 5+ years delivering full-flow physical design for large-scale, high-performance SoCs at advanced nodes.
- Proven track record driving designs through the complete RTL-to-GDSII flow including synthesis, placement, CTS, routing, extraction, and verification.
- Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for multi-voltage domains.
- Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and MCMM STA sign-off timing analysis.
- Demonstrated ability to implement aggressive PPA optimization techniques across the entire physical design cycle.
- Strong command of power grid design, EMIR analysis, and ECO generation for robust silicon integrity.
- Skilled in employing best-known methods to optimize and handle DFT structures within block-level implementations.
- Expert-level command of industry-standard tool suites for end-to-end physical design flows.
- Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations.
Nice to Have
- M.S./Ph.D. preferred.
- Specialized experience in physical design of blocks containing high-speed SerDes IPs such as PCIe, CXL, C2C, and Die-to-Die interfaces.
Technical Stack
- TCL
- Python
- Perl
Benefits & Compensation
- Compensation: $136,000 USD - $218,500 USD for Level 3, and $168,000 USD - $264,500 USD for Level 4.
- Eligible for equity.
- Highly competitive salaries.
- Comprehensive benefits package.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
