Spreedly is looking for a Staff Engineer to join our team. You will lead static timing analysis setup, reviews, and sign-off for complex SoCs. You'll drive timing closure at the full-chip level and collaborate with cross-functional teams to resolve constraint conflicts and ensure robust timing strategies.

What You'll Do

Lead static timing analysis (STA) setup, reviews, and sign-off for multi-mode, multi-corner, and multi-voltage domain designs.
Develop and maintain constraints for block and SoC hierarchical designs across multiple modes.
Drive timing closure at the full-chip level, supporting physical design teams on block and subsystem convergence.
Collaborate with design, DFT, IP, and PD teams to resolve constraint conflicts and ensure robust timing strategies.
Guide clock tree synthesis (CTS) methodologies and provide strategic input to implementation teams.
Manage ECO generation and implementation methodologies to achieve timing closure.
Support gate-level simulations and verification enablement.
Create automation scripts to enhance STA methodologies and processes.

What We're Looking For

7–14 years of experience in synthesis and STA for full-chip sign-off and tape-outs.
Hands-on expertise with both block-level and full-chip timing constraints for hierarchical designs.
Strong knowledge of DFT constraints and ASIC physical design implications on timing.
Experience with Synopsys/Cadence tools, advanced node technologies, and variation/aging-aware design sign-off.
Solid understanding of timing budgets, CTS methodologies, and power/timing/area trade-offs.
Proficiency in scripting languages such as Perl, TCL, or Python.
Familiarity with multi-voltage designs using CPF/UPF and power analysis with PTPX.
Knowledge of VHDL/Verilog constructs, RTL debugging, and IP-level verification.
Excellent communication skills, with the ability to explain complex technical issues clearly.
A collaborative mindset with enthusiasm for problem-solving and teamwork.

Technical Stack

Tools: Synopsys/Cadence
Scripting: Perl, TCL, Python
Power Formats: CPF/UPF
Power Analysis: PTPX
HDL: VHDL/Verilog

Team & Environment

You will collaborate with cross-functional teams including design, DFT, IP, and PD teams.

Benefits & Compensation

Competitive compensation package.
Restricted Stock Units (RSUs).
Opportunities for advanced education and access to eLearning providers.
Comprehensive medical insurance and wellness benefits.
Educational assistance and loan support programs.
Office-provided lunch and snacks.
Inclusive and flexible work environment supporting both personal and professional success.