Altera is looking for a Pre-Si Verification Engineer to join a team dedicated to verifying new and existing features for Intel's next-generation CPU IP. You will be responsible for exhaustively validating the RTL implementation of new architecture and microarchitecture capabilities using a combination of standalone and top-level test environments as well as formal verification, ensuring a bug-free final design.
What You'll Do
- Develop pre-Si validation test plans and test scenarios to prove the correctness of the design.
- Develop components for a simulation-based environment: bus functional models, trackers, checkers, scoreboards, and testbenches.
- Perform and debug digital simulations, and drive to closure of bugs.
- Develop functional coverage and achieve coverage goals.
- Work closely with design engineers, micro-architects, and other team members to ensure high quality of test plans, functional coverage, and tests.
- Deliver high-quality output against deadlines and work effectively in a cross-site team environment.
What We're Looking For
- A Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or a related field.
- Intermediate to advanced English level.
- 3 years of experience working with in-depth computer architecture knowledge.
- 3 years of experience working with hardware description languages (such as VHDL, Verilog or System Verilog).
- 3 years of experience with test bench development using System Verilog UVM/OVM, checker development, coverage analysis, failure debug, and root cause analysis.
Nice to Have
- A Master's degree in electrical engineering, Computer Engineering, Computer Science, or a related field.
- Experience with Intel Architecture ISA and system architecture, x86 assembly language.
- Experience with industry standard formal verification tools such as Jasper Gold, IFV, Questa Formal, VC Formal.
- Proficiency in at least one programming/scripting language such as C/C++, Perl, Ruby, Python, and Unix (Linux).
Technical Stack
- VHDL, Verilog, System Verilog, System Verilog UVM/OVM
- C/C++, Perl, Ruby, Python
- Unix (Linux)
- Intel Architecture ISA, x86 assembly language
- Jasper Gold, IFV, Questa Formal, VC Formal
Team & Environment
You will be part of the E-Core CPU team, a CPU Core development team.
Work Mode
This is a hybrid position based in Guadalajara, Mexico.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
