About the Role
Role details below.
Responsibilities
- Implement key aspects of the ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification
- Optimize designs for performance, reliability, and manufacturability
- Perform chip-level power integrity analysis across multiple voltage domains (IR drop, signal EM, and power EM)
- Work on digital implementation embedded in analog environments
- Collaborate with global cross-functional teams including analog designers and verification engineers
Requirements
- Experience in ASIC Physical Design
- Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks
- Knowledge of power integrity analysis (IR drop and electromigration)
- A team player who enjoys working in an international, collaborative environment
Nice to Have
- Analog Layout experience is a plus
Work Arrangement
Remote (Worldwide)
