The Foundational IP Integration QA Lead will oversee QA efforts for Foundational IP integration across all process nodes, ensuring robust validation and efficiency improvements. This role includes managing QA progress, enhancing automation and test coverage, and serving as Timing Owner for Full Chip Reference Design Development.
Responsibilities
- Monitor deliveries and QA requirements for FIP platforms and reference design flows.
- Evaluate FIP integration QA processes, identify gaps, and implement thorough QA checks in collaboration with the FIP Platform and QA team.
- Enhance QA coverage for the FIP platform by introducing new tests and eliminating redundant ones to increase efficiency.
- Collaborate with DTP teams to identify and integrate best practices in QA automation and workflow design.
- Partner with DA engineers to define automation needs and supervise the implementation of automation solutions.
- Coordinate with FIP Platform and QA team members to track and record QA progress for all FIP releases.
- Serve as Timing Owner during Full Chip Reference Design Development.
- Lead technical coordination with internal teams and EDA vendors to resolve issues and enhance design productivity and efficiency.
Requirements
- Bachelor of Science in Electronic, Electrical, or Computer Engineering, or equivalent, with at least 8 years of experience in SoC, analog, IP, or ASIC design or methodology development.
- Skilled in using synthesis, place-and-route tools, and physical design flows, with strong knowledge in optimization, timing convergence, IR drop analysis, DRC resolution, and low-power verification.
- Proficient in static timing analysis and creating timing constraints.
- Experience completing the full RTL to GDS design cycle for SOCs and testchips, including signoff and tapeout phases.
- Experienced in Unix/Linux environments and shell scripting.
- Demonstrated experience in reliability verification processes.
Nice to Have
- Master’s degree in Electronic, Electrical, or Computer Engineering, or equivalent, with 6 years of relevant experience, or a Ph.D. with 4 years of relevant experience.
- Knowledge of advanced process nodes and associated design methodologies.
- Strong scripting skills in PERL and TCL for automating design tasks.
- Proven problem-solving abilities and experience working effectively in team environments.
- High initiative, persistence, and capability to manage ambiguity and perform under pressure with multiple deadlines.
Tech Stack
synthesis tools, place-and-route tools, physical design flows, static timing analysis, constraints development, RTL to GDS design cycle, Unix/Linux, shell programming, PERL, TCL, EDA tools
Work Arrangement
onsite — Malaysia, Penang
Team
Part of the FIP Platform and QA team within the Design Technology Platform (DTP) group in Foundry Technology Development (Foundry TD)
