Digital Equipment Engineering for RF Payloads – This role supports engineering activities at ESA’s ESTEC facility in the Netherlands, focusing on digital systems within RF payloads. You will deliver technical expertise throughout all stages of project lifecycles, from concept to implementation, contributing to both operational missions and research initiatives.
Key Responsibilities
- Support ESA projects and studies with engineering analysis and technical documentation
- Conduct simulations to evaluate end-to-end system performance
- Lead in-house design assessments and trade-off analyses for digital equipment
- Develop, validate, and maintain software tools and internal databases
- Model and test digital hardware components, including FPGAs, ASICs, and DSPs
- Collaborate with laboratory teams to plan and execute hardware and software testing
- Define technical requirements and statements of work for industrial contracts
- Review deliverables from external partners and advise technical officers
- Stay current with advancements in digital signal processing, machine learning, and RF system design
- Contribute to technology roadmaps and participate in technical reviews with industry and academia
Required Qualifications
- Master’s degree in Telecommunications, Electronics, or Computer Science Engineering
- Proven experience in digital equipment design for RF payloads, including simulation and programming
- Solid understanding of digital processing architectures, SDR, and RF system interfaces
- Hands-on knowledge of high-speed data conversion, FPGAs, DSPs, and CPUs
- Experience in signal processing, data compression, encryption, and control unit development
- Familiarity with specification and validation of digital components in collaboration with technical teams
Preferred Skills
- Background in digital architecture design for Earth Observation, Telecom, or Navigation payloads
- Experience developing and optimizing algorithms for modulation, beamforming, AI/ML, and error correction
- Skill in evaluating performance metrics under system constraints like latency and power
- Proficiency in FPGA/ASIC design workflows and languages such as VHDL and Verilog
Work Environment & Benefits
- Hybrid model: 3 days onsite, 2 days remote (within the Netherlands)
- Flexible scheduling with core hours
- 30 days of paid annual leave plus agency closures
- Competitive salary and fully covered comprehensive health insurance
- Strong pension plan with no employee contribution
- Career growth through Coursera access and dedicated training funds
- Travel allowance and full relocation support
