Astera Labs is hiring a Design Verification Director to lead verification for a flagship product in our portfolio. This hands-on leadership role involves driving the verification strategy and ensuring first-pass silicon success for complex SoC designs in server, storage, and networking domains.
What You'll Do
- Own and drive the end-to-end verification methodology for a specific product line.
- Lead, mentor, and grow a team of engineers, fostering technical excellence and innovation.
- Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.
- Champion advanced methodologies like UVM, formal verification, and AI-augmented flows to accelerate coverage closure and improve efficiency.
- Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.
- Represent verification in executive reviews, customer engagements, and industry forums.
- Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.
What We're Looking For
- Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
- 15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
- Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.
- Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
- Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.
- Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).
- Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
- Strong background in writing assertions, cover properties, and analyzing coverage data.
- Experience in developing VIP abstraction layers to simplify and scale verification deployments.
Nice to Have
- Expertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.
- Experience with buffering, queuing, and QoS in complex NoC-based SoCs.
- System-level performance analysis on switching fabrics.
- Familiarity with AI-driven verification methodologies and workforce transformation strategies.
Technical Stack
- UVM
- Formal verification
- AI-augmented flows
- PCIe
- CXL
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply.
