Axelera AI is hiring a Principal Engineer - Silicon Logical Design to drive technical leadership across our digital design organisation. In this hands-on role, you will own and deliver organisation-wide, multi-year technical goals for AI accelerator SoCs from specification through tape out, combining deep technical expertise with influence to drive execution, quality, and innovation.
What You'll Do
- Own organisation-wide, multi-year technical direction across teams and silicon programs.
- Define system-level architectures for AI accelerator SoCs aligned to long-term strategy.
- Make high-impact technical decisions under ambiguity and align the organisation behind them.
- Drive system and micro-architecture specs through high-quality RTL implementation.
- Deliver large, high-risk programs under tight schedules.
- Lead validation, bring-up, debug, and silicon issue root-cause analysis.
- Partner across architecture, verification, physical design, software, product, and DFT.
- Translate technical capability into product roadmaps and customer value.
- Identify and execute company-wide opportunities across organisational boundaries.
- Set and enforce standards for RTL quality, reuse, and design reviews.
- Establish the bar for engineering processes, quality, and execution.
- Introduce mechanisms to measure and communicate customer impact.
- Mentor senior engineers and provide direct, constructive feedback.
- Scale knowledge through documentation, talks, and technical guidance.
- Hire and attract senior talent in partnership with leadership.
- Drive business outcomes through influence and cross-functional leadership.
- Optimise for the broader organisation, not local teams.
- Communicate clearly, lead difficult decisions, and encourage bold, accountable execution.
- Uphold and shape Axelera’s culture and values.
What We're Looking For
- Extensive experience in digital and logical design for complex SoCs with multiple successful tape outs.
- Strong expertise in RTL and micro architecture development (SystemVerilog and Verilog).
- Experience with large scale SoC integration including CPUs, accelerators, memory subsystems, and interconnects.
- Solid understanding of performance, power, and area trade offs in advanced process nodes.
- Experience working closely with verification and physical design teams to achieve functional and timing closure.
- Track record of delivering organisation wide, multi year technical initiatives.
- Demonstrated ability to influence technical direction without direct management authority.
- Strong communication skills and the ability to operate at both strategic and hands on technical levels.
Nice to Have
- Experience with AI and ML accelerators, GPUs, NPUs, or high performance compute architectures.
- Familiarity with industry standard interconnects such as AXI and NoC architectures.
- Knowledge of low power design techniques and multi clock or multi voltage systems.
- Experience with silicon bring up, post silicon debug, and root cause analysis.
- Experience working in a startup or fast scaling environment.
- History of contributing to industry standards, patents, or technical publications.
Technical Stack
- SystemVerilog
- Verilog
- AXI
- NoC architectures
Team & Environment
You’ll join the digital design organisation, collaborating cross-functionally across architecture, verification, physical design, software, product, and DFT.
Benefits & Compensation
- Pension plan
- Extensive employee insurances
- Option to get company shares
- Open culture supporting creativity and innovation
- Collaborative ownership and freedom with responsibility
Work Mode
This is a hybrid position open to candidates in Leuven (Belgium), Amsterdam (Netherlands), Eindhoven (Netherlands), Zurich (Switzerland), Florence (Italy), Milan (Italy), and Bristol (United Kingdom).
At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team.
