The IC Design Engineer at Broadcom will play a key role in designing and optimizing the digital portions of high-performance SerDes IP for advanced communication systems. This position involves deep technical engagement in digital and mixed-signal design, system-level integration, and silicon validation for high-speed interfaces.
What You'll Do
- Understanding the architecture of transmitters, receivers, equalizers, clock recovery circuits, and other digital components of high-performance SerDes supporting various communication standards.
- Design, simulate, and optimize SerDes-related digital components taking into consideration factors such as data rate, jitter, and power consumption.
- Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design.
- Collaborate with the broader engineering team to ensure robust signal integrity and power integrity in SerDes designs.
- Collaborate with cross-functional teams, including physical design, system engineering, and validation teams, to ensure seamless integration of SerDes IP into larger systems.
- Prepare and maintain comprehensive design documentation, including specifications, microarchitecture, and test plans.
- Support silicon bring-up and debug efforts.
What We're Looking For
- BS +12 Years of relevant industry experience.
- Must have strong Logic Design, RTL coding (Verilog HDL) skills.
- Must understand low power design and validation techniques including UPF.
- Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks.
Nice to Have
- Advanced degree preferred.
- Proven experience in SerDes design with a focus on high-speed communication interfaces.
- Familiarity of analog and mixed-signal circuit design principles.
- Thorough understanding of the impact of process technologies on SerDes design.
- Excellent problem-solving skills and ability to troubleshoot complex mixed-signal IP blocks.
- Familiarity with system-level considerations in high-speed communication interfaces.
Technical Stack
- Verilog HDL
- UPF
- Logic synthesis
- Timing closure analysis
- Clock/Reset domain crossing checks
- Lint
Team & Environment
- Cross-functional collaboration with physical design, system engineering, and validation teams
Benefits & Compensation
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
- Other leaves of absence
Compensation includes a salary range of $141,300 - $226,000, equity in accordance with equity plan documents and equity award agreements, and a discretionary annual bonus in accordance with relevant plan documents.
Work Mode
Not specified.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
