About the Role
Role details below.
Responsibilities
- Perform digital design and RTL coding using Verilog or System Verilog
- Integrate modules at SoC level
- Work hands-on in the development cycle, especially in the frontend domain until tapeout
- Conduct RTL coding, CDC (Clock Domain Crossing), Lint, synthesis, STA (Static Timing Analysis), and DFT (Design for Testability)
- Debug and fix functional issues in RTL
- Develop scripts to automate frequently used processes
- Validate all digital design functionality on silicon
- Debug and find innovative solutions to design issues
Requirements
- Experience in digital design and RTL coding using Verilog or System Verilog
- Hands-on involvement in the frontend development cycle up to tapeout
- Skills in RTL coding, CDC, Lint, synthesis, STA, and DFT
- Ability to debug and fix functional issues in RTL
- Experience in validating digital design functionality on silicon
- Scripting skills to automate processes
Additional Information
- Role is targeted at graduate-level candidates
- Focus on digital design and RTL implementation in SoC environments
- Involves full frontend digital design flow up to tapeout
- Requires hands-on debugging and automation skills
