Join Altera, an Intel company, as a CPU RTL Design Engineer to design and develop CPU logic, ensuring power, performance, and area optimization. You will be at the forefront of shaping CPU architecture and microarchitecture, influencing the development of processors for SoC solutions.
What You'll Do
- Develop logic design, RTL coding, and simulation for CPUs, creating functional units, cell libraries, and CPU IP blocks for integration into full-chip designs.
- Define and contribute to the architecture and microarchitecture features of the CPUs being designed.
- Apply strategies and tools to write RTL code, optimizing logic for power, performance, area, and timing goals.
- Collaborate on verification planning and implementation to validate design features.
- Document microarchitectural specifications (MAS) for CPU features and provide support to SoC customers.
- Debug and resolve complex cross-domain issues spanning RTL, tools, and software.
What We're Looking For
- Bachelor's in Computer Engineering or Electrical Engineering Computer Architecture with 4+ years of experience or Master's degree with 3+ years of experience.
- 4+ years experience with hardware description languages like Verilog and System Verilog and familiarity with tools like VCS or QuestaSim.
- 3+ years programming experience in Perl, Python, or C/C++, with advanced debugging skills in complex environments.
- 3+ years experience designing coherent systems with advanced queues/pipelines, external bus interfaces, snoop filters, and L2 cache featuring ECC, MCA, and repair mechanisms.
- 3+ years experience scripting in an interpreted language (e.g., TCL, Perl, Python, Ruby) and/or using AI to generate/edit scripts.
Nice to Have
- Ability to effectively communicate complex technical concepts to cross-disciplinary teams and stakeholders.
- Proven problem-solving skills and experience working in collaborative, fast-paced environments.
- Experience in modern, energy-efficient/low-power logic design techniques.
- Good communication skills.
Technical Stack
- Languages: Verilog, System Verilog, Perl, Python, C/C++, TCL, Ruby
- Tools: VCS, Questasim
Team & Environment
You will join as part of the Silicon and Platform Engineering Group (SPE).
Benefits & Compensation
- Compensation Range: $122,440.00 - $232,190.00 USD
- Health, retirement, and vacation benefits
- Competitive pay and stock bonuses
Work Mode
This role follows a hybrid work model in the United States, with locations in Phoenix, Arizona and Austin, Texas.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
