Join Innatera Nanosystems as a Staff SoC Verification Engineer. You will develop and maintain SystemVerilog/UVM-based verification environments for our ultra-efficient neuromorphic processors, driving methodology improvements and ensuring coverage closure for chip release-readiness.
What You'll Do
- Develop and maintain SystemVerilog/UVM-based verification environments at both module and SoC level.
- Write test sequences, define functional coverage models, and ensure coverage closure.
- Debug simulation results using waveform tools and collaborate with design teams to resolve issues.
- Drive constrained-random stimulus generation and continuous improvements in our verification methodology.
- Apply modern EDA tools and automate verification flows to maximize speed and quality.
- Contribute to quality assurance, release-readiness, and design-test alignment for every chip.
What We're Looking For
- 8+ years of digital verification.
- 4+ years of constrained-random verification with UVM.
- 2+ years of embedded C development for SoC verification.
- Experience designing verification architecture from design specifications and creating test plans.
- Ability to translate functional requirements into functional coverage models.
- Skilled in constrained-random stimulus generation and coverage analysis/closure.
- Strong expertise in root-cause analysis and debugging SystemVerilog RTL.
- Proficiency in scripting with Python or similar languages.
- Solid experience with Linux, bash, or equivalent environments.
- Proficient with commercial EDA tools.
- Experience collaborating effectively with cross-functional teams.
- Hands-on experience with UVM verification architecture and vertical reuse of lower-level UVCs/environments.
- Skilled in mixed-language simulation and system modeling.
- Experience with effort estimation, project planning, scheduling, and tracking.
- Proven ability to lead and mentor a small team.
Nice to Have
- Experience with SystemC for modeling and simulation.
- Knowledge of UPF and low-power verification methodologies.
- Exposure to formal verification techniques.
- Hands-on experience with FPGA validation and bring-up.
- Experience with full-chip emulation and bring-up.
- Familiarity with OpenOCD/GDB for software-driven verification.
- Experience in SystemVerilog RTL design.
Technical Stack
- Verification: SystemVerilog, UVM
- Software: C, Python
- Environment: Linux, bash
- Tools: EDA tools, SystemC, UPF, OpenOCD, GDB
Benefits & Compensation
- Competitive salary.
- Pension plan.
- Flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme).
- A generous holiday scheme.
- A collaborative, ambitious team with the freedom to innovate.
- An inclusive culture that values openness, curiosity, and personal growth.
- Office perks like fresh fruit, snacks, and an on-site gym.
- Statutory commuting/home allowance.
Work Mode
This is a hybrid position based in The Netherlands.
Innatera is proud to be an equal opportunity employer. We welcome applicants of all backgrounds and experiences and are committed to building a diverse, inclusive, and respectful workplace. All qualified applicants will receive consideration for employment without regard to race, ethnicity, religion, gender, gender identity or expression, sexual orientation, disability, age, or other protected characteristics.
