Join Axelera AI as a Senior/Staff DFT Engineer and play a key role within our multicore in-memory-compute SoC team. You will design, implement, and validate test solutions for complex SoCs, collaborating with talented engineers across Europe.
What You'll Do
- Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault simulation flows.
- Collaborate with RTL, verification, and physical design teams to integrate DFT solutions efficiently.
- Support silicon bring-up and debug, helping to optimize test coverage and yield.
- Contribute to methodology improvements and share best practices with team members.
What We're Looking For
- Minimum of 5 years in DFT engineering, preferably with complex SoC projects.
- Skills: SystemVerilog RTL, TCL, Python, Unix/Linux workflows.
- Core Knowledge: Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification.
- Tools: Siemens, Synopsys, or Cadence DFT tool experience.
- Strong problem-solving skills, collaboration, and passion for semiconductor innovation.
Nice to Have
- Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, timing analysis.
Technical Stack
- SystemVerilog RTL
- TCL
- Python
- Unix/Linux
- Siemens/Synopsys/Cadence DFT tools
Team & Environment
You will join a multicore in-memory-compute SoC team within a world-class organization of over 220 employees.
Benefits & Compensation
- Attractive compensation package
- Pension plan
- Extensive employee insurances
- Option to get company shares
Work Mode
This is a hybrid role open in Leuven, Belgium; Amsterdam, Netherlands; Eindhoven, Netherlands; Zurich, Switzerland; Florence, Italy; Milan, Italy; Bristol, United Kingdom.
We embrace equal opportunity and hold diversity in the highest regard, cultivating a warm and inclusive environment.
