Responsibilities
- Develop architectures for L2 and L3 switching fabrics that support Time-Sensitive Networking standards to guarantee predictable latency for critical automotive communications.
- Lead the integration of PCIe Gen 5 and Gen 6 interfaces to enable fast, reliable connections between system-on-chips, AI processors, and storage components, including virtualization through SR-IOV.
- Implement hardware-based safety features such as error correction, parity checking, built-in self-test, and end-to-end protection to meet ASIL-B and ASIL-D safety requirements in routing and bus subsystems.
- Design interfaces linking Ethernet and PCIe controllers with internal network-on-chip and coherent interconnect fabrics to efficiently transport data from ADAS sensors like cameras and LiDAR.
- Create hardware architectures that enable secure virtualization and on-board communication protection, ensuring network resources are shared safely while defending against cyber threats.
- Define comprehensive clocking, reset, and power management strategies that support automotive environmental conditions and enable fast boot-up times for responsive vehicle operation.
