Responsibilities
- Lead synthesis from RTL to gate-level for advanced multi-die microcontroller units using standard industry tools
- Improve circuit performance in timing, power, and area while meeting requirements of mature semiconductor nodes
- Lead static timing analysis and achieve timing closure across multiple operating conditions and modes
- Ensure final sign-off meets specifications for timing, power consumption, and signal integrity
- Collaborate with RTL, DFT, and physical design teams to resolve critical timing challenges
- Manage full-chip timing constraints and drive design optimizations to reach convergence
- Develop and maintain synthesis and timing closure strategies suited for cost-driven MCU products
- Assess EDA tools and implementation flows to enhance productivity and reduce turnaround time
Work Arrangement
Hybrid
Other
- The company promotes equal opportunity and affirmative action, ensuring a workplace that respects diversity and prohibits discrimination based on sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military or veteran status, or other legally protected categories.
- Designated office days are Tuesday, Wednesday, and Thursday, supporting innovation, team collaboration, and ongoing professional development.
