What You'll Do
Own the end-to-end physical design flow, starting from netlist and progressing through to GDSII delivery. Develop and optimize floor plans to meet power, performance, and area goals. Execute automated place and route tasks with precision, ensuring design integrity throughout.
Drive timing closure using sign-off methodologies, addressing setup, hold, and skew requirements. Perform comprehensive IR and electromigration (EM) analyses to guarantee power delivery stability and long-term reliability. Conduct thorough layout verification to meet foundry-specified design rules.
Validate design equivalence through formal verification techniques. Support final tape-out procedures, ensuring all deliverables are complete, accurate, and production-ready.
Requirements
- Proven experience in full-chip physical design implementation
- Strong understanding of floor planning, placement, and routing strategies
- Expertise in timing closure methodologies and tools
- Experience with IR/EM analysis and sign-off criteria
- Proficiency in layout verification and formal verification flows
- Familiarity with tape-out processes and deliverables
Benefits
Access to advanced design tools and fabrication technologies. Opportunities to work on complex, high-performance semiconductor products. Support for professional growth and technical development within a globally recognized engineering environment.
