Altera is seeking a PDK Development Engineer to develop and deliver high-quality Process Design Kits for Intel's advanced process technologies. Your work will enable design teams to bring leadership products to market faster by collaborating with domain experts across Technology Development, EDA vendors, and product design teams to create technology collaterals, models, and EDA tool enablement.
What You'll Do
- Develop physical layout verification software for DRC, LVS, and RC extraction to support the latest Intel technologies and microprocessor designs.
- Develop runsets using industry standard EDA tools including Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus.
- Coordinate the development of technology features, create QA plans, and drive test-case development with relevant stakeholders.
- Support PDK development and Intel design teams to debug and enhance runset quality, runtime, and usability.
- Develop ESD protection verification on emerging PERC verification tools.
- Understand circuit topology and various ESD protection schemes, implementing them in verification runsets.
- Model parasitic elements related to interconnects and understand their extraction and verification in PERC.
- Develop state-of-the-art PERC ESD verification workflows.
- Work with multiple EDA companies to co-develop extraction solutions.
- Develop new extraction techniques for upcoming technology features and validate EDA solutions against models and measured data.
- Develop extraction runsets and flows using popular extraction solutions like StarRC, Quantus, and xACT.
- Work with various solvers and popular 2D and 3D electromagnetic packages.
What We're Looking For
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related STEM field.
- 6+ months of work or educational experience with Unix/Linux operating systems.
- 6+ months of work or educational experience programming or scripting in at least one of: C++, Python, Ruby, Perl, Tcl, or SKILL.
- 6+ months of work or educational experience with CMOS device physics, process technology, or design rules.
Nice to Have
- Experience with software repository management tools like Git.
- Knowledge of DRC, LVS, or Extraction runsets.
- Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling.
- Familiarity with VLSI design processes, reliability verification, ESD concepts, standard cell libraries, and memory architectures.
- Familiarity with custom layout design of analog, RF, or digital circuits on advanced process technology nodes.
- Working knowledge of EDA tools including Synopsys ICV, Siemens/Mentor Calibre, Cadence Pegasus, Virtuoso or Custom Compiler, Cadence Innovus, Synopsys Fusion Compiler, or Siemens Aprisa tools.
Technical Stack
- Operating Systems: Unix/Linux
- Languages: C++, Python, Ruby, Perl, Tcl, SKILL
- Tools: Git, Synopsys ICV, Siemens/Mentor Calibre, Cadence Pegasus, StarRC, Quantus, xACT, Raphael, HFSS, Fast Henry, Quick Cap, Virtuoso, Custom Compiler, Cadence Innovus, Synopsys Fusion Compiler, Siemens Aprisa
Team & Environment
You will be part of the Process Design Kit group within the Design Technology Platform organization at Intel Foundry. DTP is a key pillar enabling Intel to deliver winning products in the marketplace.
Work Mode
This position follows a hybrid work model based in Penang, Malaysia.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
