Apply on company website Austin, Texas; Sunnyvale, California On-site Full-time $250K – $315K

Neurophos is hiring a Staff Compiler Engineer

About Neurophos The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach. Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference. We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years. Join us and shape the future of computing! Position Overview: We are seeking a talented ML Compiler Engineer to join our engineering team and lead the development of our compiler. This role focuses on compiler development for our novel LLM accelerator architecture. This is one of several software stacks that seamlessly bridge high-level AI workloads with our custom hybrid optical-electronic compute hardware, enabling customers to realize game-changing performance. Location: San Jose, CA or Austin, TX. Full-time onsite position. Key Responsibilities: - Design and implement toolchains for our custom LLM accelerator architecture - Develop optimization strategies that bridge software algorithms to hardware implementations - Design and implement custom compiler components, including IR dialects, graph transformations, and lowering passes - Optimize computational graphs and memory access patterns for our hardware architecture - Integrate with existing ML frameworks (e.g., PyTorch, JAX, Triton). - Build and maintain test infrastructure to ensure compiler correctness and performance Qualifications: - Master's degree in Computer Science or related field - 5+ years of experience in compiler development - Expert-level proficiency in Python and C - Experience with hardware compilers - Familiarity with Large Language Model architectures and their computational requirements - Hands-on experience with compiler frameworks and code optimization techniques - Deep understanding of computer architecture, memory hierarchies, and parallel computing concepts - Experience with AI/ML accelerators (GPUs, TPUs, FPGAs) and their programming models Preferred Skills: - PhD in Computer Science or related field - 7+ years of industry experience - Strong background in graph theory and graph transformations in a compiler or optimization context; MLIR experience is a plus - Experience writing programs that parse, analyze, and mutate programs as abstract syntax trees - Experience in instrumenting and debugging parallel programs - Experience with structured, human-supervised AI/agentic coding workflows - Experience with LLM quantization techniques and model optimization - Experience with high-performance computing and low-latency system design - Familiarity with deep learning frameworks and neural network optimization Technical Skills - Programming Languages: Python and C (essential), Assembly - Compiler Frameworks: LLVM, MLIR, GCC, custom backend development - Graph Theory: Graph algorithms, graph rewriting systems, DAG optimization - AST Processing: Parsing, analysis, and transformation of abstract syntax trees - Testing & QA: pytest, GoogleTest, or similar frameworks; static analysis tools - CI/CD: Jenkins, GitHub Actions, GitLab CI, or similar systems - LLM Technologies: Transformer architectures, attention mechanisms, quantization techniques - Development Tools: CMake, Git, Docker - Parallel Tools: Profilers, debuggers, and instrumentation for parallel/concurrent programs Technical Environment - Languages: Python and C (primary), Assembly for low-level optimization - Compiler Tools: LLVM, MLIR, GCC, custom compiler backends - Testing: Automated test suites, continuous integration pipelines - Frameworks: PyTorch/JAX/Triton integration, custom inference engines - Focus Areas: Compiler backend development, optimization passes, hardware-software co-design What We Offer This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world. Benefits Join a team that invests in your future and your well-being. At Neurophos, we offer: - 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions. - Unlimited PTO. No rigid vacation banks, just a focus on delivery. - 401(k) matching and stock option opportunities to ensure our success is your success. - Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance. - Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t. Compensation Range: $250K - $315K
Job Details
Location Austin, Texas; Sunnyvale, California
Work mode On-site
Employment Full-time
Salary $250K – $315K
Department Engineering Software
Posted 6 months ago
Application On company website
About company
Neurophos

The most efficient AI chip on the planet.

Neurophos compresses a rack into the size and power draw of a single GPU, delivering 0.47 ExaOPS and 300 TOPS/W with its Optical Processing Units (OPUs).

The company has achieved a breakthrough by shrinking photonic tensor cores by 10,000x, enabling terawatt compute with gigawatt power. This leap is equivalent to 30 years of transistor scaling and is protected by 300 patents.

Neurophos' technology allows for massive compute efficiency, reducing the need for thousands of GPUs and hundreds of nuclear plants down to just a few OPUs and 10 nuclear plants, revolutionizing the future of AI hardware.

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