About the Role
Lead the architectural definition and integration of SOC-IP components, aligning with system requirements and silicon implementation constraints.
Responsibilities
- Define architectural specifications for SOC-IP blocks used in system-on-chip designs
- Collaborate with design and verification teams to ensure IP functionality meets requirements
- Evaluate performance, power, and area trade-offs during IP integration
- Ensure compliance with interface standards and interoperability across subsystems
- Develop models and prototypes to validate architectural choices
- Support synthesis, timing closure, and physical implementation of IP modules
- Work closely with software teams to enable early software development
- Document architectural decisions and interface definitions
- Guide IP reuse strategies across product lines
- Identify and mitigate risks in IP integration early in the development cycle
- Interface with external IP providers for licensing and integration support
- Analyze technology scaling impacts on IP performance and reliability
- Contribute to development of design methodologies and best practices
- Ensure security and safety requirements are addressed in IP architecture
- Participate in cross-functional reviews of SOC and subsystem designs
- Drive improvements in design efficiency and verification coverage
- Assess third-party IP for technical fit and integration complexity
- Maintain alignment with roadmap goals and product timelines
- Optimize for testability and diagnostic capabilities within IP blocks
- Support post-silicon validation and debug of integrated IP
Nice to Have
- Master's degree in electrical or computer engineering
- Experience with high-speed interface IP such as PCIe, USB, or Ethernet
- Background in AI/ML accelerator architectures
- Knowledge of RISC-V or other open instruction set architectures
- Experience in automotive or safety-critical domains
- Familiarity with formal verification techniques
- Contributions to industry standards or open-source hardware projects
- Experience with cloud-scale infrastructure or data center applications
- Published work or patents in SOC or IP design
- Leadership in cross-organizational technical initiatives
Compensation
Competitive salary with performance-based incentives
Work Arrangement
Hybrid work model with primary location in Austin, TX
Team
Part of the Silicon Architecture group within the Engineering division
Technology Focus
Current projects emphasize scalable interconnect fabrics, low-latency memory subsystems, and power-gated IP blocks for edge computing applications
Collaboration Model
- Work in agile pods with mixed hardware, software, and systems engineers using iterative development cycles
- Regular syncs with product management and customer engineering teams
Available for qualified candidates requiring sponsorship
