Sandisk is hiring a Senior Technologist, Mask Design Engineering ((Extensive IC Layout Design-22 years of expertise in custom/AMS across analog, digital, and mixed-signal domain)

Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑Signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success. Key Responsibilities Advanced Layout Design & Optimization Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies. Design Verification & Sign‑off Leadership Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rigorous verification and closure strategies. Power Distribution & Floor planning Architecture Architect full‑chip power distribution networks and floorplans to optimize electrical performance, minimize parasitic’s , and reduce die size. Provide guidance on placement, routing, and hierarchical layout planning. Cross‑Functional Technical Leadership Collaborate with Design Engineering (DE), Integration (INTEG), and Process Technology teams across global sites to resolve design issues, align methodologies, and ensure seamless integration. Drive technical convergence on topics such as buffer topology, layout methodologies, and design‑rule interpretation. Methodology Development & Continuous Improvement Define and enhance layout methodologies, automation flows, and best practices to improve productivity, consistency, and design quality. Champion innovation in layout automation and process optimization. Technical Mentorship & Review Provide technical direction to senior layout engineers, conduct critical block reviews, and elevate team capability through mentorship and knowledge sharing.