Join Cadence as a Senior Principal Firmware Engineer and become part of a dynamic team developing physical layer IP for industry-standard high-speed serial-link protocols. Your work will directly impact Die-2-Die and Chiplet Interconnects, taking firmware from architectural development through to customer deployment.
What You'll Do
- Collaborate with UCIe PHY digital and mixed signal architects to define firmware functions and sequences, contributing to architecture and implementation.
- Build system-level prototype control software to develop and validate adaptation, equalization, and control algorithms for high-speed UCIe IPs.
- Validate developed firmware in emulation-based models and simulations.
- Implement assigned firmware features, working closely with verification and validation teams to ensure functionality and robustness.
- Support the Validation team during electrical and system characterization in post-silicon testing, identifying and resolving firmware and hardware functionality and performance issues.
- Assist Product Engineering, System Validation, and Design teams in debugging IP issues during customer deployment and provide hot fixes.
- Create and maintain comprehensive documentation related to firmware design, development, bug fixes, and compliance testing.
What We're Looking For
- A B.Tech with 14 years or an M.Tech with 12 years in Electrical or Electronics Engineering.
- Solid programming knowledge in C/C++ and Python.
- Understanding of wireline communication principles and digital signal processing techniques.
- Strong problem-solving and communication skills.
- Proven, hands-on experience developing for hardware-based DSP acceleration engines.
- Expertise in code development, debugging, and profiling using IDEs.
Nice to Have
- Experience with silicon validation processes and debug.
- Familiarity with digital verification environments and tools.
Technical Stack
- C/C++
- Python
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