Austin, Texas; Sunnyvale, California On-site Full-time USD 225,000 – 270,000 / year

Neurophos is hiring a Senior Manager of Board Design

Responsibilities

  • Oversee complete PCB development cycles for all OPU product boards, including carrier boards, interposers, driver boards, and evaluation platforms.
  • Establish board architecture, layer configurations, and design rules for high-speed digital interfaces and precision analog/optoelectronic circuits.
  • Conduct and lead reviews of schematics and layouts, ensuring compliance with manufacturability, testability, and signal integrity standards.
  • Lead board bring-up, debugging, and performance characterization for mixed-signal systems, developing repeatable electrical and optical test methods.
  • Manage libraries for schematic blocks, footprints, and simulation models across digital, analog, and optoelectronic components.
  • Integrate silicon photonic ICs, laser drivers, TIAs, and high-speed data converters into board designs interfacing with optical engines.
  • Work with optical and optomechanical teams to convert system-level optical requirements into actionable PCB design specs.
  • Develop and execute qualification plans for optoelectronic subsystems, including eye diagrams, BER testing, and optical power validation.
  • Monitor advancements in silicon photonics packaging and evaluate implications for future board-level architectures.
  • Recruit, onboard, and grow a team of board design engineers.
  • Define team strategy and allocate resources across multiple simultaneous board development programs.
  • Provide technical guidance, set performance expectations, and conduct regular evaluations to support professional development.
  • Promote a design culture emphasizing simulation-first approaches, thorough design reviews, and systematic failure analysis.
  • Coordinate with ASIC, firmware, test, and systems teams to ensure board designs support automated testing, known-good-die workflows, and in-field diagnostics.
  • Manage relationships with PCB manufacturers, contract assemblers, and component vendors, driving NPI timelines, DFM improvements, yield gains, and cost reductions.
  • Deliver regular updates on board program progress, critical path risks, and staffing needs to senior engineering leadership.

Benefits

  • Full coverage of health insurance premiums for employee and dependents, including contributions to a Health Savings Account.
  • Unlimited paid time off with no fixed accrual system, emphasizing results over vacation tracking.
  • 401(k) matching and eligibility for stock options to align personal and company success.
  • Comprehensive voluntary benefits including dental, vision, life, hospital, critical illness, and accident insurance.
  • Flexible benefits package allowing customization based on personal needs, with cash options for unused plans.

Work Arrangement

On-site

Work Arrangement

San Jose, CA, Austin, TX

Other

  • Full-time onsite position.
  • Position located in San Jose, CA or Austin, TX.
About company
Neurophos

The most efficient AI chip on the planet.

Neurophos compresses a rack into the size and power draw of a single GPU, delivering 0.47 ExaOPS and 300 TOPS/W with its Optical Processing Units (OPUs).

The company has achieved a breakthrough by shrinking photonic tensor cores by 10,000x, enabling terawatt compute with gigawatt power. This leap is equivalent to 30 years of transistor scaling and is protected by 300 patents.

Neurophos' technology allows for massive compute efficiency, reducing the need for thousands of GPUs and hundreds of nuclear plants down to just a few OPUs and 10 nuclear plants, revolutionizing the future of AI hardware.

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Job Details
Department Engineering; Product Engineering
Posted 2 months ago