Responsibilities
- Building context and forming new relationships during onboarding
- Taking ownership of test development for assigned block or IP
- Debugging verification failures
- Understanding and debugging gate-level simulations (GLS)
- Working as part of a highly skilled verification team
- Learning from experienced colleagues
- Evolving tasks based on skills and professional development
Tech Stack
UVM, System Verilog, C, RTL, GLS
Benefits
- Equal employment opportunities
- No discrimination or harassment based on race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by law
- Opportunity to work with cutting-edge technology and complex technical challenges
- Open knowledge sharing and supportive team culture
Work Arrangement
On-site — Oulu, Finland
Additional Information
- The position is located in Oulu, Finland
- Alif Semiconductor provides equal employment opportunities and prohibits discrimination and harassment
- Policy applies to all terms and conditions of employment including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training
