NVIDIA is looking for a Senior ASIC Power Engineer to craft the power architecture for its leading-edge products. You will join the NVIDIA Power Architecture Group, handling the full range of power-related activities across the product lineup.
What You'll Do
- Join the team handling ASIC energy evaluation, power architecture, low power development, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation.
- Support power analysis by aiding in the architecture, creation, verification, and correlation of power estimation models and tools.
- Architect and build system-level power features to optimize dynamic and leakage power dissipation for different use cases.
- Work on power verification, including structural, functional, and power-aware verification by developing test plans, writing test cases, building test bench components, and owning verification convergence across RTL, Gates, and Silicon.
- Validate the efficiency of power features on silicon, conduct studies, and contribute to Performance/Watt improvement ideas.
- Help develop power management solutions and foster innovation in energy efficiency throughout the product portfolio.
What We're Looking For
- B.Tech./M.Tech (or equivalent experience) with over 5 years of experience in power analysis, power development, power-aware verification, UPF methodologies, and power correlation.
- Solid understanding of all power aspects, including full-chip power modeling, transistor-level leakage and dynamic characteristics in VLSI circuits.
- Strong fundamentals in digital build flow and Verilog (especially low power RTL development).
- Familiarity with low power build techniques such as multi-VT, clock gating, power gating, voltage islands, and Dynamic Voltage-Frequency Scaling (DVFS).
- Solid experience in power estimation methods, processes, and algorithms.
- Working experience with scripting languages like Python is a must.
- Prior experience writing SW-driven power virus tests and silicon debug is necessary.
- Must be an excellent collaborator and prepared to work with international groups from varied cultural origins in a dynamic environment.
Nice to Have
- Experience in power supply and supply noise analysis and reduction.
- Good debugging and problem-solving skills.
- Strong communication abilities and the capability to work well with others.
- Solid programming skills, ideally in C++ & Python.
- Knowledge of lab equipment for power measurements, including oscilloscopes or DAQs, along with the capability to troubleshoot board-level power issues.
Technical Stack
- Verilog
- UPF methodologies
- Python
- C++
Team & Environment
You will be part of the NVIDIA Power Architecture Group.
Benefits & Compensation
- Highly competitive salaries
- Comprehensive benefits package
- Eligible for equity and benefits
- Compensation: 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
Work Mode
This is an onsite position located in Santa Clara, CA.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
