Responsibilities
- Establish microarchitectural specifications for advanced digital blocks and subsystems
- Contribute directly to RTL implementation of critical functional units
- Lead architectural decisions balancing performance, power, area, and testability
- Develop, review, and merge robust RTL code for synthesis and verification
- Own integration at both block and full-chip levels, resolving system-level interface conflicts
- Guarantee compliance with linting, clock domain crossing, and synthesis standards
- Optimize RTL for downstream physical and timing implementation
- Implement and manage scan chains, test structures, and test coverage completion
- Execute, validate, and troubleshoot logic equivalence checks between RTL and gate-level netlists
- Create and verify timing constraints in SDC format and achieve timing closure
- Manage timing and functional engineering change orders throughout the design cycle
- Lead preparation for design signoff across lint, CDC/RDC, synthesis, LEC, and timing
- Ensure all design deliverables meet functional correctness, timing, power, and test targets
- Support post-silicon validation, debugging, and root cause investigation
- Collaborate with verification, physical design, DFT, and firmware groups
- Coordinate design execution with verification strategies and implementation constraints
- Serve as the technical liaison connecting front-end design and back-end implementation teams
Benefits
- Stock option award included as part of compensation
- Full benefits suite including medical, dental, vision, and 401(k) plan
Work Arrangement
Hybrid
Team
Reports to Head of Engineering
Work Arrangement
- This position is hybrid, requiring three days per week on-site at company headquarters in Vancouver, WA (Greater Portland Area) or Chandler, AZ.
- Remote flexibility may be available for highly qualified candidates located in Silicon Valley, CA.
