Responsibilities
- Develop test plans for highly configurable intellectual property blocks that enable communication between components in SoC, chiplet, and multi-chiplet environments
- Implement verification environments using UVM and SystemVerilog, including test cases, checkers, and scoreboards
- Partner with software engineering teams to define and build adaptable test bench frameworks
- Collaborate with design teams on test planning, debug of failures, and achieving coverage goals
Work Arrangement
Remote (City/Region)
Responsibilities
- Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
- Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
- Collaborate with software teams to define and implement configurable test benches
- Work with design teams on test plans, failure debug, coverage, etc.
