Role Overview
The Director of Silicon Logical Design will lead and scale the digital design organization at Axelera AI, driving the architectural realization, RTL implementation, and integration of complex AI accelerator SoCs from specification through tape-out. This is a hands-on leadership role requiring deep technical expertise and strong people leadership in a fast-paced startup environment.
Responsibilities
- Lead and grow the silicon logical (digital) design team, including RTL, integration, and design methodology
- Drive the translation of system and micro-architecture specifications into high-quality RTL implementations
- Own the end-to-end logical design execution for one or more SoCs, from concept through tape-out
- Partner closely with architecture, verification, physical design, DFT, software, and product teams to ensure robust and scalable designs
- Define and enforce best practices for RTL quality, coding standards, reuse, and design reviews
- Oversee block-level and top-level integration, ensuring performance, power, area, and schedule targets are met
- Support bring-up, debug, and silicon validation activities, including root-cause analysis of silicon issues
- Contribute to long-term technology and roadmap planning, including IP strategy and future architecture directions
- Mentor and develop engineers, fostering a culture of technical excellence, ownership, and collaboration
Required Qualifications
- Extensive experience in digital / logical design for complex SoCs, with multiple successful tape-outs
- Proven ability to lead and grow high-performing silicon design teams
- Strong expertise in RTL and micro-architecture development (SystemVerilog / Verilog)
- Experience with large-scale SoC integration, including CPUs, accelerators, memory subsystems, and interconnects
- Solid understanding of performance, power, and area trade-offs in advanced process nodes
- Experience working closely with verification and physical design teams to achieve functional and timing closure
- Strong communication skills and the ability to operate at both strategic and hands-on technical levels
Preferred Qualifications
- Experience with AI/ML accelerators, GPUs, NPUs, or high-performance compute architectures
- Familiarity with industry-standard interconnects (e.g., AXI, NoC architectures)
- Knowledge of low-power design techniques and multi-clock / multi-voltage systems
- Experience with silicon bring-up, post-silicon debug, and root-cause analysis
- Experience working in a startup or fast-scaling environment
Technical Stack
SystemVerilog, Verilog, RTL, SoC integration, AXI, NoC architectures
Work Mode
Hybrid work model with options to work from office or remotely across European countries. Office locations include Leuven (Belgium), Amsterdam and Eindhoven (Netherlands), Zurich (Switzerland), Florence and Milan (Italy), and Bristol (UK). Flexible arrangements support remote work from any European country or relocation to Italy or the Netherlands.
Company Culture
Axelera AI fosters an innovative, creative, and collaborative environment built on ownership, responsibility, and technical excellence. The company values diversity, inclusion, and equal opportunity, supporting an international and distributed team culture that empowers every individual.
EEO Statement
Axelera AI wholeheartedly embraces equal opportunity and holds diversity in the highest regard. The company is committed to cultivating a warm and inclusive environment that empowers and celebrates every team member, welcoming applicants from all backgrounds.
