Responsibilities
- Support functional verification of high-performance CPUs used in general computing and artificial intelligence workloads.
- Assist in creating test plans and test environments for instruction set architecture and microarchitectural features.
- Analyze and debug RTL implementations, contributing to meaningful design improvements in chip development.
- Develop scalable tools and stimulus generation code applicable across pre-silicon simulation and post-silicon validation phases.
Compensation
Compensation for all interns ranges from $50/hr to $70/hr, including base and variable components.
Work Arrangement
On-site — Santa Clara, CA, Austin, TX
Team
Not applicable
Other
- This position requires on-site presence with a 40-hour workweek at either Santa Clara, CA or Austin, TX.
- The internship is scheduled for the Fall 2026 semester.
- Intern compensation ranges from $50 to $70 per hour, combining base and variable pay targets.
- Final offer amounts depend on individual factors such as experience, skills, education, background, and location.
- The company provides a competitive compensation and benefits package and is an equal opportunity employer.
- Employment is conditional upon the candidate's eligibility to access U.S. export-controlled technology.
- Compliance with U.S. Export Administration Regulations (EAR) is required, particularly regarding technology transfer to nationals of specific countries (e.g., EAR Country Groups D:1, E1, E2).
- These regulations apply regardless of the candidate's location, whether in the U.S. or abroad.
- Since the role involves access to controlled information, systems, or technologies, employment may depend on citizenship, permanent residency status, or obtaining prior approval from the U.S. Commerce Department or relevant federal agency.
- If U.S. export laws prevent employment, any offer extended will be withdrawn.
Not applicable
