Responsibilities
- Support the validation of next-generation RISC-V and AI accelerator system-on-chip designs for functional accuracy and resilience.
- Build and enhance modern verification environments by creating tests and checkers, and assess coverage to finalize complex digital IP and subsystem sign-off.
- Create and sustain SystemVerilog/UVM testbenches for IP blocks and subsystems, covering stimulus generation, checking logic, and scoreboarding.
- Formulate and refine verification test strategies derived from architectural and microarchitectural specifications, emphasizing edge-case testing and coverage completeness.
- Develop both constrained-random and directed test scenarios, execute regression campaigns, and debug failures in coordination with RTL design teams.
- Evaluate functional and code coverage data to detect gaps and recommend targeted tests or assertions to achieve full coverage closure.
- Assist in developing automation tools, scripts, Makefiles, CI integrations, and dashboards to boost verification efficiency and reduce debug cycles.
- Collaborate with architecture, design, performance, and validation teams to align on expected behavior and sign-off requirements.
- Be evaluated based on achieved coverage metrics, the quality and reproducibility of identified bugs, and the reliability of the verification infrastructure contributed to.
Work Arrangement
Hybrid — Boston, MA
Other
- This position operates in a hybrid format from the Boston, MA office.
- The expected duration is a minimum of 3 months, with possible extension up to 6 months.
- Hiring for U.S.-based roles follows seasonal cycles: Winter term (Jan–Apr work, Sept–Dec recruit), Summer term (May–Aug work, Oct–Apr recruit), Fall term (Sept–Dec work, Jan–Aug recruit).
- These hiring timelines are approximate and subject to change.
